Develop block-level and full-chip level verification environment for complex, mixed signal integrated circuits; define verification strategy; develop and implement test plans; create overall infrastructure verification methodology; design, develop, implement, and maintain test benches; write and execute test cases; identify bugs; develop solutions to correct problems; and provide guidance and support to Verification Engineer. Requirements – Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field of study and three years of verification experience or Bachelor’s degree and five years of post-baccalaureate and progressive experience in verification. Three years of work experience in ASIC verification using SystemVerilog, UVM/VMM/AVM, C, and Perl/Shell.
Please refer to Job Number ESE15-2901 when submitting resume.
Submit resume to:
Esencia Technologies, Inc.
2041 Mission College Blvd., Suite 100
Santa Clara, CA 95054
ATTN: Human Resources-Job No. ESE15-2901
E-mail: hr@esenciatech.com
