Analyze and design complex, multi-million gate integrated circuits using electronic design automation tools; conduct physical design, floor planning, and place and route; perform logic synthesis, power analysis, and static timing analysis; integrate full chip; implement block level intellectual property; perform physical verification of integrated circuit layout design to ensure chips meet design specifications and are absent of physical defect affecting functionality and performance; carry out formal verification and testing activities; troubleshoot problems; and provide support to less experienced design engineers. Requirements – Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field of study and three years of experience with integrated circuit design or Bachelor’s degree and five years of post-baccalaureate and progressive experience in integrated circuit design. Three years of integrated circuit design using Synopsys electronic design automation tools Design Compiler, Formality, IC Compiler, and PrimeTime.
Please refer to Job Number ESE15-5206 when submitting resume.
Submit resume to:
Esencia Technologies, Inc.
2041 Mission College Blvd., Suite 100
Santa Clara, CA 95054
ATTN: Human Resources-Job No. ESE15-5206
E-mail: hr@esenciatech.com