This is an opening at a major fortune 500 company with an immediate need.
Job Requirements and Qualification
You must have a BSEE or MSEE with at least 5+ years of applicable experience. Demonstrate successful results for multiple ASIC programs, is required. Strong written / verbal communication skills are a must, as you will be working, influencing and collaborating with teams in distributed locations. You will need to be very organized with solid understanding of Synopsys and Cadence design tools and flows.
Minimum Requirements
- Direct hands-on experience on top level complex SoC floorplan
- Hands on experience with Synopsys Jupitor XP and ICC tols
- Integration of Various IP’s including: MIPI, USB, I2C, GPIO, DDR etc
- Ability to work with cross-functional teams to troubleshoot floorplan and packaging issues
- Familiarity with ASIC design flows for deep sub micron technologies
- Familiarity with deep sub-micron design rules
Preferred Requirements
- Familiarity with image processing is a strong plus
Responsibilities
In this role, the candidate will work with the designers to integrate the design into floorplan. The Candidate needs to understand the complexity of integrating various IP’s and IO pad ring generation. A candidate will work with the ASIC design team to understand the IP area and SoC gate area to come up with an optimized die-size.
Responsibilities include:
Generate/Optimize pad ring, core by working with cross-functional teams including front-end designs, package design, and System board design teams. A candidate will design the floorplan by integrating the gate-level netlist and timing constraints. Estimate/Optimize chip / die size. Work with engineers to identify IO ring and IO voltage domains. Familiarity with EM (ElectroMigration) and SSO (Simultaneously Switching Output) checks. Support synthesis teams with feedback from the Place and Route perspective and integration.
This Job is located in Silicon Valley / San Jose, CA & Metropolitan Statistical Area. Candidate must have the legal right to work in the USA .
Please refer to Job Number ESE13-0101 when submitting resume.
Submit resume to:
Esencia Technologies, Inc.
2150 North First Street, Suite #680
San Jose, CA 95131
ATTN: Human Resources-Job No. ESE13-0101
E-mail: hr@esenciatech.com
