Job Description
Design test plan to verify complex IP cores for audio and video processing; define test coverage; develop verification environment and test suites for full chip and block level; verify designs at system and block level; develop test bench; write test cases for system level test bench; run test cases; and debug test failures.
Job Requirements and Qualification
Bachelor’s degree in Electrical Engineering, Electronics Engineering, Telecommunication Engineering, or related field of study and five years of progressive experience in verification. ASIC design verification, Verilog, SystemVerilog, OVM/UVM/VMM, Perl, C++, and VCS. Work in San Jose, CA & Metropolitan Statistical Area.
Please refer to Job Number ESE12-0501 when submitting resume.
Submit resume to:
Esencia Technologies, Inc.
2150 N. First Street, Ste. 680
San Jose, CA 95131
ATTN: Human Resources-Job No. ESE12-0501
E-mail: hr@esenciatech.com
