Verify double data rate (DDR) memory controller subsystem intellectual property of complex system-on-chip (SoC); perform functional coverage models; design and develop efficient, reusable verification environment; architect OVM based test bench; create and implement detailed verification test plan; determine appropriate tests; write test cases; execute testing; identify and isolate design issues; enhance current verification infrastructure; and debug issues with DDR memory controller subsystem. Requirements – Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field of study and three years of experience with DDR verification or Bachelor’s degree and five years of post-baccalaureate and progressive experience in DDR verification. Three years of work experience with DDR verification using SystemVerilog, OVM based verification methodology, C/C++, and Perl/JavaScript.
Please refer to Job Number ESE15-4802 when submitting resume.
Submit resume to:
Esencia Technologies, Inc.
2041 Mission College Blvd., Suite 100
Santa Clara, CA 95054
ATTN: Human Resources-Job No. ESE15-4802
E-mail: hr@esenciatech.com