Verify the digital design of complex system on chip (SoC); define test coverage; design verification plan; create functional coverage models; write assertions; develop tests to study new features added to the core; architect and design reusable test benches; write and execute test cases; and architect regression framework. Requirements – Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field of study and three years of experience with SoC verification or Bachelor’s degree and five years of post-baccalaureate and progressive experience in SoC verification. Three years of experience with SoC digital design verification using System Verilog and UVM.
Please refer to Job Number ESE16-9503 when submitting resume.
Submit resume to:
Esencia Technologies, Inc.
3945 Freedom Circle, Suite 360
Santa Clara, CA 95054
ATTN: Human Resources-Job No. ESE16-9503
E-mail: hr@esenciatech.com