Design and develop Design for Test (DFT) and Design for Manufacturing (DFM) techniques for integrated circuits; architect DFT and DFM features; design develop test programs to verify manufacturing faults in integrated circuits; implement test architecture and test logic; perform ATPG (Automatic Test Pattern Generation); simulate ATPG test vectors; review schematic and layout of test board and probe cards; determine test coverage; improve test coverage and test processes; create test plans, test scripts, and test fixtures; and diagnose and debug defects in production. Requirements – Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field of study and three years of experience with integrated circuit testing or Bachelor’s degree and five years of post-baccalaureate and progressive experience in integrated circuit testing. Three years of work experience with DFT, MBIST, ATPG, Perl/Shell, and TCL.
Please refer to Job Number ESE16-1901 when submitting resume.
Submit resume to:
Esencia Technologies, Inc.
3945 Freedom Circle, Suite 360
Santa Clara, CA 95054
ATTN: Human Resources-Job No. ESE16-1901
E-mail: hr@esenciatech.com