Perform static timing analysis for complex integrated circuits; responsible for timing closure activities of the entire design cycle; generate timing constraints; maintain timing accuracy with additional processes and functionality; close timing; minimize engineering change order iterations; perform leakage recovery; fix signoff violations; develop constraints for functional and design for testing modes; tailor constraints for synthesis, implementation, and signoff; and support design automation and design implementation teams on constraints related issues during timing closure. Requirements – Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field of study and three years of experience with static timing analysis or Bachelor’s degree and five years of post-baccalaureate and progressive experience in static timing analysis. Three years of experience with static timing analysis, Primetime SI, C, Shell, and TCL.
Please refer to Job Number ESE15-9604 when submitting resume.
Submit resume to:
Esencia Technologies, Inc.
2041 Mission College Blvd., Suite 100
Santa Clara, CA 95054
ATTN: Human Resources-Job No. ESE15-9604
E-mail: hr@esenciatech.com
