Plan and execute functional verification of complex digital ASIC/FPGA designs in the areas of networking, host bus adapters, and graphics processors using advanced verification methodologies; develop and modify test bench; write and port test cases; run regression tests; compile and report test results; debug failure; perform code coverage; verify integration; write scripts to enhance the verification process; and provide guidance and support to verification engineers. Requirements – Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field of study and three years of experience in functional verification or Bachelor’s degree and five years of post-baccalaureate and progressive experience in functional verification. Three years of work experience in functional verification using Verilog, System Verilog, Perl, and UVM/OVM/VMM/AVM.
Please refer to Job Number ESE15-1256 when submitting resume.
Submit resume to:
Esencia Technologies, Inc.
3945 Freedom Circle, Suite 360
Santa Clara, CA 95054
ATTN: Human Resources-Job No. ESE15-1256
E-mail: hr@esenciatech.com
